Speeding time to market, the Cadence 3D-IC reference flow, featuring the Integrity 3D-IC platform, has been certified for UMC’s chip stacking technologies. UMC’s hybrid bonding solutions support the integration across a broad range of nodes that are suitable for edge AI, image processing, and wireless communication applications.
Using UMC’s 40-nm low-power process as a wafer-on-wafer stacking demonstration, the two companies collaborated to validate key 3D-IC features in the design flow. Cadence’s Integrity 3D-IC platform combines system planning, chip and packaging implementation, and system analysis in a single platform.
The reference flow is built around a high-capacity, multi-technology hierarchical database. Multiple chiplets in a 3D stack can be designed and analyzed together through integrated early analyses of thermal management, power, and static timing. The reference flow also enables system-level layout versus schematic (LVS) checking, electrical rule checking, and design rule checking.
In addition to the Integrity 3D-IC platform, the reference flow includes the following Cadence products: Innovus, Quantus, Tempus, Pegasus, Voltus, and Celsius. To learn more about Cadence 3D-IC design solutions, click here.
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